1. Field of the Invention
The invention generally relates to communication in computer systems. More specifically the invention relates to a method and system for communication in a computer system that employs Peripheral Component Interconnect Express (PCIe) links.
2. Description of the Related Art
The Peripheral Component Interconnect Express (PCIe) is a general purpose Input/Output (I/O) interconnect used for communication between two or more devices inside a computer. The examples of the devices may include a graphics processor and a chipset. A computer system that employs PCIe communicates by sending packets. The packets are formed in three discrete logical layers that include the transaction layer, the data link layer and the physical layer. Each packet has a header corresponding to these layers and a data payload portion. The header contains information that may include format, type, and attribute of a packet, address/routing information, encoding information, and data protection. The data payload portion contains data required by a device.
In conventional systems, a read completion packet is generated by a chipset that comprises a root-complex, upon completion of a memory read request issued by an endpoint device. The read completion packet includes a conventional read completion header portion and a data payload portion. The conventional read completion header portion includes a physical layer header that is two bytes long, a data link layer header that is six bytes long and a transaction layer header that is twelve bytes long.
Additionally, in conventional systems, a memory write request packet is generated by the endpoint device when issuing a memory write request to the root-complex. The memory write request packet includes a conventional memory write request header portion and a data payload portion. The conventional memory write request header portion includes a physical layer header that is two bytes long, a data link layer header that is six bytes long and a transaction layer header that is twelve bytes long.
These packets consume a large amount of bus bandwidth of computer systems employing PCIe links and limit the bus throughput efficiency of such systems. There is therefore, a need for a method and system that can increase the bus throughput efficiency of computer systems employing PCIe links.